It is common practice to use a bus master to move data from a master agent to main memory and to move data from a main memory to a master agent. A computer system that comprises a plurality of master agents may use a plurality of bus masters. In some cases, there can be one bus master for each master agent.
One of the most popular memory devices in use today is Dynamic Random Access Memory (DRAM). The latency for reading a desired item of data from DRAM memory depends upon how many DRAM banks (or DRAM pages) are presently open. The condition that exists when a desired item of data is located in an opened DRAM bank is referred to as a “Page Hit.” The latency for a “Page Hit” is approximately two (2) or three (3) DRAM clock cycles.
The condition that exists when a desired item of data is not located in an opened DRAM bank is referred to as a “Page Miss.” The latency for a “Page Miss” is much higher than the latency for a “Page Hit.” This is because the DRAM controller has to close one of the presently opened DRAM banks, open the desired DRAM bank, and then read the data from the newly opened DRAM bank.
In a multiple-master computer system, the individual bus masters access the DRAM memory concurrently. That is, the requests from the bus masters that are sent to the individual DRAM banks are interlaced. This causes the “Page Hit” rate and the DRAM interface throughput to be significantly reduced. Therefore in a multi-master computer system the bandwidth of the main memory interface (e.g., DRAM controller) becomes the performance bottleneck of the system.
It would be desirable to have a multi-master computer system that enables bus masters to access main memory in a more efficient manner.
It would be desirable to have a multi-master computer system that reduces the latency required for a bus master to access main memory.
It would be desirable to have a multi-master computer system that increases the throughput of the main memory interface.